This thesis presents the design and verification of a custom RISC-V processor implemented on Field-Programmable Gate Array (FPGA) technology. The project optimized hardware efficiency, achieved stable 50 MHz performance, and enabled software execution using SystemVerilog design and official benchmarks. It demonstrates how open-source hardware enables affordable, customizable computing solutions.

Flash memory stores essential data but degrades with repeated use, limiting reliability in long-term applications like cars and satellites. Inspired by biological circadian rhythms, this research introduces “recovery periods” for memory cells to rest and repair. The approach improves flash memory lifespan up to ninefold, enabling more durable and dependable storage systems.

This research improves data center energy efficiency by analyzing processor instruction sequences. By identifying and fusing recurring instruction patterns, existing general-purpose processors can execute workloads more efficiently. Even small gains at the instruction level can significantly reduce energy consumption, operating costs, and carbon emissions across large-scale data centers.